`timescale 1ns / 1ps
module top_8x3;
    reg [7:0] Inputs;
    wire [2:0]Outputs;

    initial begin
        Inputs = 8'b1000_0000;
        # 2 Inputs = 8'b0100_0000;
        # 2 Inputs = 8'b0010_0000;
        # 2 Inputs = 8'b0001_0000;
        # 2 Inputs = 8'b0000_1000;
        # 2 Inputs = 8'b0000_0100;
        # 2 Inputs = 8'b000_00010;
        # 2 Inputs = 8'b0000_0001;
        # 2 Inputs = 8'b0000_0000;
        # 2 Inputs = 8'b0101_0110;
        # 2 Inputs = 8'b001_01000;
        # 2 $finish;
    end

    priority_encoder pe(.Inputs(Inputs),.Outputs(Outputs));
 	initial
  	begin
    	$dumpfile("test.vcd");
    	$dumpvars(0, pe);
  	end 
endmodule




module priority_encoder(Inputs,Outputs);
    input [7:0]Inputs;
    output reg [2:0]Outputs;
    always @(*)begin
        if(Inputs[7]==1'b1)Outputs = 3'b111;
        else if (Inputs[6]==1'b1)Outputs = 3'b110;
        else if (Inputs[5]==1'b1)Outputs = 3'b101;
        else if (Inputs[4]==1'b1)Outputs = 3'b100;
        else if (Inputs[3]==1'b1)Outputs = 3'b011;
        else if (Inputs[2]==1'b1)Outputs = 3'b010;
        else if (Inputs[1]==1'b1)Outputs = 3'b001;
        else Outputs = 3'b000;
    end
endmodule
